The present disclosure relates to semiconductor devices and methods for fabricating the same. For semiconductor device density enhancement, a multigate transistor has been suggested as one scaling technology according to which a multi-channel active pattern (or silicon body) in a fin or nanowire shape is formed on a substrate, with gates then being formed on a surface of the multi-channel active pattern. A multigate transistor may allow easy scaling, as it uses a three-dimensional channel. Further, current control capability can be enhanced without requiring increased gate length of the multigate transistor. Furthermore, it may be possible to effectively suppress short channel effect (SCE), which is a phenomenon in which the electric potential of a channel region is influenced by the drain voltage.